In the present art for multichip modules which involve either a metallized ceramic (MC) module or a metallized multilayer ceramic (MLC) module, it was found that both suffer from limitations for extension to future cost/performance application. The MC module at present is a single layer of metallurgy on the surface of a ceramic substrate with a limited extension to being made double sided because of the scarcity of wiring vias available. Also, I/O pins are limited especially in a multichip application since each chip site on the module removes one to five staked pin via positions. Further decrease in pin pitch to compensate for this has to date not been practical because of the industry standardization on a 100 mil pin grid which is violated only in a few special situations. This also contributes to a relatively low logic chip density possibility which is counter to both cost and performance. For high performance, the MC module was limited to single chip applications.
The MLC module also has its own set of limitations. While higher chip density and wireability are possible, the cost is higher and the performance is limited. First, the cost is higher due to the large amount of work content in its production. The signal lines are screened resulting in very low line density and, therefore, large numbers of required signal layers. Further, for high performance application, the screening process is pushed to its limits, presently only 4 mil width lines, resulting in excessive touch up steps and more expense. The MLC module is considered by the industry to be a relatively expensive package.
With regard to performance, the electronic signals propogate now internally through the ceramic which has a dielectric constant of approximately 9. This results in a propogation delay equal to 3 times that of air, the square of the dielectric constant. Further delays result from pulse degration caused by skin effect which is a function of the line resistance. The MLC is forced to use the higher resistance refractory metals that can withstand high ceramic fusion temperatures. Typically, moly conductor of a 4 mil width will have ten times the resistance per unit length than that of a 1 mil copper MC line. This skin effect can add up to 50% more delay to a signal for path lengths in the range of a multichip module, and also restricts circuit designers who must allow for higher signal resistances in their net design. Finally, a very important requirement in high performance is engineering change capability. Internal ceramic deletes of signal lines is, at best, very difficult.